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FDS6912
January 2000
FDS6912
Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET
General Description
These N-Channel Logic Level MOSFETs have been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. These MOSFETs feature faster switching and lower gate charge than other MOSFETs with comparable RDS(ON) specifications. The result is a MOSFET that is easy and safer to drive (even at very high frequencies), and DC/DC power supply designs with higher overall efficiency.
Features
RDS(ON) = 0.028 @ VGS = 10 V * 6 A, 30 V. RDS(ON) = 0.042 @ VGS = 4.5 V. * Optimized for use in switching DC/DC converters with PWM controllers * Very fast switching. * Low gate charge
D1 D1 D2 D2 S1 G1
5 6 7
Q1
4 3 2
Q2
SO-8
S2
8
1
G2
Absolute Maximum Ratings
Symbol
VDSS VGSS ID PD Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed
TA=25 C unless otherwise noted
o
Parameter
Ratings
30 20
(Note 1a)
Units
V V A W
6 20 2
Power Dissipation for Dual Operation Power Dissipation for Single Operation
(Note 1a) (Note 1b) (Note 1c)
1.6 1 0.9 -55 to +150 C
TJ, Tstg
Operating and Storage Junction Temperature Range
Thermal Characteristics
RJA RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
(Note 1a) (Note 1)
78 40
C/W C/W
Package Marking and Ordering Information
Device Marking FDS6912
2000 Fairchild Semiconductor Corporation
Device FDS6912
Reel Size 13''
Tape width 12mm
Quantity 2500 units
FDS6912 Rev E (W)
FDS6912
Electrical Characteristics
Symbol
BVDSS BVDSS TJ IDSS IGSSF IGSSR
TA = 25C unless otherwise noted
Parameter
Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage, Forward Gate-Body Leakage, Reverse
(Note 2)
Test Conditions
VGS = 0 V, ID = 250 A ID = 250 A, Referenced to 25C VDS = 24 V, VGS = 20 V, VGS = -20 V VGS = 0 V TJ = 55C VDS = 0 V VDS = 0 V
Min
30
Typ
Max Units
V
Off Characteristics
20 1 10 100 -100 mV/C A nA nA
On Characteristics
VGS(th) VGS(th) TJ RDS(on)
Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain-Source On-Resistance On-State Drain Current Forward Transconductance
VDS = VGS, ID = 250 A ID = 250 A, Referenced to 25C VGS = 10 V, VGS = 4.5 V, ID = 6 A TJ = 125C ID = 4.9 A VDS = 5 V ID = 6 A
1
2 -5 0.024 0.034 0.035
3
V mV/C
0.028 0.048 0.042
ID(on) gFS
VGS = 10 V, VDS = 10 V,
20 20
A S
Dynamic Characteristics
Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance
(Note 2)
VDS = 15 V, f = 1.0 MHz
V GS = 0 V,
740 170 75
pF pF pF
Switching Characteristics
td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge
VDD = 15 V, VGS = 10 V,
ID = 1 A, RGEN = 6
8 13 18 8
16 24 29 16 10
ns ns ns ns nC nC nC
VDS = 10 V, VGS = 5 V
ID = 6 A,
7 3.8 2.5
Drain-Source Diode Characteristics and Maximum Ratings
IS VSD Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.3 A
(Note 2)
1.3 0.75 1.2
A V
Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design.
a) 78/W when 2 mounted on a 0.5in pad of 2 oz copper
b) 125/W when mounted on a 0.02 2 in pad of 2 oz copper
c) 135/W when mounted on a minimum mounting pad.
Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%
FDS6912 Rev E (W)
FDS6912
Typical Characteristics
30
VGS = 10V
24 I , DRAIN-SOUR CE CURREN T (A)
6.0V 5.0V 4.5V
2 1.8 1.6 V GS = 4.0V
18
4.0V
12
1.4 1.2 1
4.5V 5.0V
3.5V
6.0V 7.0V 10V
D
6
3.0V
0 0 1 1 2 2 V DS, D RAIN-SOUR CE VOL TAGE (V) 3 3
0.8 0 10 20 30 40 50
ID, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with Drain Current and Gate Voltage.
8
1.6 1.5 DRAIN-SOURCE ON-RESISTANCE 1.4 1.3 1.2 1.1 1.0 0.9 0.8
R DS(ON) ,NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
ID = 6.3A V GS =10V
R DS(ON) ,()
I = 3.0A
7
D
6
5
TA = 125 C
4
o
3
2
0.7 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (C) 125 150
1 2 4 V
GS
25 o C
6 ,GATE-SOURCE VOLTAGE (V) 8 10
Figure 3. On-Resistance Variation withTemperature.
20
Figure 4. On-Resistance Variation with Gate-to-Source Voltage.
100
VDS = 5V
I D , DRAIN CURRENT (A) 15
TJ = -55C
25C 125C
10
VGS = 0V
TA = 125 C 1 25 C
o
o
10
0.1 0.01
-55 C
o
5
0.001 0.0001
0
0 1 2 3 4 V GS , GATE TO SOURCE VOLTAGE (V) 5
0.4
0.8
1.2
1.6
V SD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature.
FDS6912 Rev E (W)
FDS6912
Typical Characteristics (continued)
10 ID = 6.3A 8 15V 6 VDS = 5V 10V

C iss
4
C oss
2

f = 1 MHz VGS = 0V
C rss
0 0 4 8 Qg, GATE CHARGE (nC) 12 16

DS

Figure 7. Gate Charge Characteristics.
100
IT LIM
Figure 8. Capacitance Characteristics.
30
20 I D , DRAIN CURRENT (A) 10
N) S(O RD
1m s
10m s
100 us
25
20
SINGLE PULSE R JA= 135C/W TA = 25
2 0.5
100
1s
VGS = 10V SINGLE PULSE RJA = 135 C/W TA = 25C
0.2 0.5 V
ms

20
15
10 s DC
10
0.05
5
0.01 0.1
DS
1 2 5 10 , DRAIN-SOURCE VOLTAGE (V)
0
0.01
0.1
1
10
100
1000

Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power Dissipation.
1
r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE
0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.0001
D = 0.5 0.2 0.1 0.05 0.02 0.01 Single Pulse P(pk)
R JA (t) = r(t) * R JA R JA = 135C/W
t1
t2
TJ - TA = P * R JA (t) Duty Cycle, D = t1 /t2
0.001 0.01 0.1 t 1, TIME (sec) 1 10 100 300
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c. Transient thermal response will change depending on the circuit board design.
FDS6912 Rev E (W)
SO-8 Tape and Reel Data and Package Dimensions
SOIC(8lds) Packaging Configuration: Figure 1.0
Packaging Description:
EL ECT ROST AT IC SEN SIT IVE DEVICES
DO NO T SHI P OR STO RE N EAR ST RO NG EL ECT ROST AT IC EL ECT RO M AGN ETI C, M AG NET IC O R R ADIO ACT IVE FI ELD S
TNR D ATE PT NUMB ER PEEL STREN GTH MIN ___ __ ____ __ ___gms MAX ___ ___ ___ ___ _ gms
Antistatic Cover Tape
ESD Label
SOIC-8 parts are shipped in tape. The carrier tape is made from a dissipative (carbon filled) polycarbonate resin. The cover tape is a multilayer film (Heat Activated Adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. These reeled parts in standard option are shipped with 2,500 units per 13" or 330cm diameter reel. The reels are dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 500 units per 7" or 177cm diameter reel. This and some other options are further described in the Packaging Information table. These full reels are individually barcode labeled and placed inside a standard intermediate box (illustrated in figure 1.0) made of recyclable corrugated brown paper. One box contains two reels maximum. And these boxes are placed inside a barcode labeled shipping box which comes in different sizes depending on the number of parts shipped.
Static Dissipative Embossed Carrier Tape
F63TNR Label Customized Label
F852 NDS 9959 F852 NDS 9959 F852 NDS 9959 F852 NDS 9959
SOIC (8lds) Packaging Information Packaging Option Packaging type Qty per Reel/Tube/Bag Reel Size Box Dimension (mm) Max qty per Box Weight per unit (gm) Weight per Reel (kg) Note/Comments Standard (no flow code) TNR 2,500 13" Dia 343x64x343 5,000 0.0774 0.6060 L86Z Rail/Tube 95 530x130x83 30,000 0.0774 F011 TNR 4,000 13" Dia 343x64x343 8,000 0.0774 0.9696 D84Z TNR 500 7" Dia 184x187x47 1,000 0.0774 0.1182
F852 NDS 9959
Pin 1
SOIC-8 Unit Orientation
343mm x 342mm x 64mm Standard Intermediate box ESD Label F63TNR Label sample
LOT: CBVK741B019 FSID: FDS9953A QTY: 2500 SPEC:
F63TNLabel F63TN Label ESD Label
(F63TNR)3
D/C1: D9842 D/C2:
QTY1: QTY2:
SPEC REV: CPN: N/F: F
SOIC(8lds) Tape Leader and Trailer Configuration: Figure 2.0
Carrier Tape Cover Tape
Components Trailer Tape 640mm minimum or 80 empty pockets Leader Tape 1680mm minimum or 210 empty pockets
July 1999, Rev. B
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape Configuration: Figure 3.0
T E1
P0
D0
F K0 Wc B0 E2 W
Tc A0 P1 D1
User Direction of Feed
Dimensions are in millimeter Pkg type SOIC(8lds) (12mm)
A0
6.50 +/-0.10
B0
5.30 +/-0.10
W
12.0 +/-0.3
D0
1.55 +/-0.05
D1
1.60 +/-0.10
E1
1.75 +/-0.10
E2
10.25 min
F
5.50 +/-0.05
P1
8.0 +/-0.1
P0
4.0 +/-0.1
K0
2.1 +/-0.10
T
0.450 +/0.150
Wc
9.2 +/-0.3
Tc
0.06 +/-0.02
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481 rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum Typical component cavity center line
0.5mm maximum
B0 20 deg maximum component rotation
0.5mm maximum
Sketch A (Side or Front Sectional View)
Component Rotation
A0 Sketch B (Top View)
Typical component center line
Sketch C (Top View)
Component lateral movement
SOIC(8lds) Reel Configuration: Figure 4.0
Component Rotation
W1 Measured at Hub
Dim A Max
Dim A max
Dim N
See detail AA
7" Diameter Option
B Min Dim C See detail AA W3
Dim D min
13" Diameter Option
W2 max Measured at Hub DETAIL AA
Dimensions are in inches and millimeters
Tape Size
12mm
Reel Option
7" Dia
Dim A
7.00 177.8 13.00 330
Dim B
0.059 1.5 0.059 1.5
Dim C
512 +0.020/-0.008 13 +0.5/-0.2 512 +0.020/-0.008 13 +0.5/-0.2
Dim D
0.795 20.2 0.795 20.2
Dim N
2.165 55 7.00 178
Dim W1
0.488 +0.078/-0.000 12.4 +2/0 0.488 +0.078/-0.000 12.4 +2/0
Dim W2
0.724 18.4 0.724 18.4
Dim W3 (LSL-USL)
0.469 - 0.606 11.9 - 15.4 0.469 - 0.606 11.9 - 15.4
12mm
13" Dia
(c) 1998 Fairchild Semiconductor Corporation
July 1999, Rev. B
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC-8 (FS PKG Code S1)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in: inches [millimeters]
Part Weight per unit (gram): 0.0774
9
September 1998, Rev. A
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM CoolFETTM CROSSVOLTTM E2CMOSTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM GTOTM HiSeCTM
DISCLAIMER
ISOPLANARTM MICROWIRETM POPTM PowerTrench QFETTM QSTM Quiet SeriesTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8
SyncFETTM TinyLogicTM UHCTM VCXTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. D

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